The capability extract shows in thirty seconds what runs as standard and what carries a surcharge.
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To the data check →Not a laminate at all but a fired inorganic plate with a metallised circuit on it. Where organic materials give up — 500 °C, extreme power density, a CTE that has to match bare silicon — ceramic is usually the only remaining option.
Two substrates dominate. Aluminium oxide (Al₂O₃) is the workhorse — 24 W/mK, inexpensive, mechanically strong. Aluminium nitride (AlN) conducts heat at 170 W/mK and above, close to aluminium metal, and costs several times as much. The metallisation route matters just as much as the substrate: DBC bonds thick copper directly for power work, thick film screens and fires conductor pastes, and thin film sputters and etches for the finest structures and tightest tolerances.
What consistently surprises people coming from FR-4 is the mechanical behaviour. Ceramic is hard, dimensionally excellent and completely brittle. It cannot be routed, drilled conventionally or flexed at all. The outline is lasered or scribed and snapped, which means the shape has to be settled early — a late outline change is a new tool, not a CAM edit.
AlN at 170 W/mK and above moves heat like metal while insulating electrically. For high power density there is often no alternative.
6 – 7 ppm/K sits close to silicon and to ceramic packages, so die can be attached directly without the thermal-cycling shear an organic substrate imposes.
Continuous service above 500 °C with no resin to soften, outgas or degrade. Downhole, aerospace and furnace electronics all end up here.
Thick film and DBC are two separate processes with separate limits. They are not interchangeable with each other, and not with the FR-4 and HDI figures elsewhere on this site.
| Parameter | Thick film | DBC |
|---|---|---|
| Max. layer count | 10 | 2 |
| Max. board thickness | 6.0 mm | 2.4 mm |
| Max. board size | 200 × 200 mm | 138 × 178 mm |
| Min. board size | 10 × 10 mm | 10 × 10 mm |
| Min. track / space | 0.25 / 0.25 mm | 0.25 / 0.25 mm |
| Min. hole | 0.10 mm | 0.10 mm |
| Aspect ratio | 8 : 1 | 8 : 1 |
| Dielectric strength | ≥ 15 kV/mm | ≥ 15 kV/mm |
| Surface finish | AgPd, AuPd | Ni plating, ENIG |
Verified factory limits for ceramic. Binding values are confirmed per project against your data.
| Property | Al₂O₃ | AlN | Note |
|---|---|---|---|
| Thermal conductivity | 24 W/mK | ≥ 170 W/mK | AlN approaches aluminium metal |
| CTE | 6.5 – 7.5 ppm/K | 4.5 ppm/K | AlN is closest to bare silicon |
| Dk (1 MHz) | 9.5 – 10 | 8.5 – 9 | High — track geometry differs sharply from FR-4 |
| Df | < 0.001 | < 0.001 | Excellent, usable to millimetre wave |
| Flexural strength | 350 – 400 MPa | 300 – 350 MPa | Strong but brittle — no plastic deformation |
| Substrate thickness | 0.25 – 1.0 mm | 0.25 – 1.0 mm | 0.635 mm is the common default |
| Metallisation | DBC / thick / thin film | DBC / thin film | Chosen by structure size and current |
| Min. track / space | 0.25 / 0.25 mm | 0.25 / 0.25 mm | Thick film and DBC — see manufacturing limits |
Guide values for pre-selection. Binding values are confirmed per project against your data.
The points below are what most often comes back as a query after data review. Settling them before layout freeze saves a loop.
Ceramic is lasered or scribed, not routed. A change to the outline late in the project means new tooling and a new sample cycle — treat the shape as frozen once samples are ordered.
Dk around 9 – 10 against 4.5 for FR-4 means a 50 Ω line on ceramic is far narrower than you are used to. Do not carry track widths over from an FR-4 design.
Brittle material concentrates stress at notches. Radius internal corners and keep cut-outs away from mounting points that will be torqued.
Ceramic will not flex to accommodate an uneven mounting surface — it will crack. Specify flatness for the heatsink and use compliant fasteners.
Start with Al₂O₃ — it handles most RF and moderate-power work at a fraction of the price. Move to AlN when the thermal calculation genuinely needs 170 W/mK and above, or when the CTE has to match bare silicon closely.
Yes, laser-drilled and filled with conductive paste, but they are expensive and the minimum diameter is larger than on FR-4. Designs that minimise via count are markedly cheaper.
The substrate itself, the metallisation process, far lower panel yields because the plates are small, and the tooling for lasering the outline. It is not a single cost driver but four.
Usually not. A hybrid build with an RF laminate only on the critical layers gets you most of the performance for a small fraction of the cost. Ceramic earns its place when heat, temperature or CTE force it.
Send us your data or a rough sketch. We check feasibility, name the cost drivers and answer within one working day.