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Ultra-fine

IC Substrate

The carrier that sits between a bare die and the main board. Structures finer than a standard HDI build, warpage held within a narrow window across the part, and a sequential build-up taken to its limit. This is the most demanding class we quote — it always starts with a feasibility review, and we publish no general limits for it.

At a glance
Min. structure on request
Build sequential HDI build-up
Microvia Ø on request
Flatness tightly toleranced
Process feasibility review first

An IC substrate does what a package does: it fans a die's I/O out from bond-pad pitch to something a board can route, and it does so in a few square millimetres. That means structures and microvias finer than a standard HDI build, and layer counts that would be unremarkable on a large board packed into a part the size of a fingernail. What is achievable depends on the design, so the values are confirmed per project rather than published here.

The dominant constraint is not the structure size but the flatness. A substrate that warps by more than a few tens of microns across its length will not accept a die reliably, and the warpage comes from the same asymmetry and copper-balance issues as any multilayer — only with far less tolerance. This is why the design conversation happens before layout rather than after data submission.

What it delivers

[ Overview ]
01

Finer than standard HDI

Structure sizes beyond the conventional etched HDI window. What is achievable is confirmed against your design in the feasibility review.

02

Sequential build-ups

Microvia layers built up stage by stage, in a part measured in millimetres. The routing density is what makes the fan-out possible.

03

Controlled warpage

Flatness held tightly enough for reliable die attach — the parameter that most often decides whether a substrate design works.

IC substrate limits

[ Specification ]
Parameter Value Note
Min. line / gap on request Confirmed per design in the feasibility review
Microvia Ø on request Laser-drilled; diameter confirmed per design
Build-up sequential HDI Number of build-up stages per design
Layer count on request Depends on die footprint and fan-out
Surface finish ENEPIG Bondable and solderable
Flatness tightly toleranced Confirmed per design in the feasibility review
Bump pitch on request Flip-chip attachment
Lead time extended Reflects the process complexity

Guide values for pre-selection. Binding values are confirmed per project against your data.

Typical applications

[ Use cases ]
Flip-chip package substrates
System-in-package carrier boards
RF module substrates for 5G front ends
Sensor packages with integrated die
Power module carriers with fine fan-out
Test and characterisation carriers for bare die

Design rules

[ Layout ]

The points below are what most often comes back as a query after data review. Settling them before layout freeze saves a loop.

01

Involve engineering before layout

Structure size, build-up and flatness interact in ways that cannot be resolved after routing. A feasibility review before layout freeze is not a formality here.

02

Design for copper balance obsessively

Warpage tolerance is a fraction of a normal board's. Copper distribution has to be balanced per layer and across the part, not just approximately symmetrical.

03

Fix the die footprint early

The bump or bond pad geometry drives the entire build-up. A change to the die pinout late in the project is a new substrate, not a revision.

04

Plan for extended lead time

The process has more steps, tighter inspection and lower yields than any other class. Schedule accordingly rather than treating it as a normal HDI order.

Rule IC substrates require a feasibility review before layout. Please involve engineering early.

Frequently asked

[ FAQ ]
Is this the same as HDI?

It is HDI taken past where normal HDI stops. The sequential build-up principle is shared, but the structure sizes and the flatness requirement are a different class — which is why the limits are confirmed per project.

What does the feasibility review cover?

Structure sizes against the process window, build-up against the routing requirement, copper balance against the warpage target, and the die attach method. It results in a build proposal you approve before layout freeze.

What quantities make sense?

Substrates are panelised in large arrays, so volume helps a great deal. Prototype quantities are possible but the per-part cost is dominated by tooling and setup.

Can I use a normal PCB house design flow?

Partly. The tools are the same, but the design rules, the tolerance stack and the DFM checks are not. Send the intended rules with the enquiry so we can flag mismatches early.

Related

[ Cross-reference ]

Does this fit your project?

Send us your data or a rough sketch. We check feasibility, name the cost drivers and answer within one working day.