Three things decide whether a layout can be built as drawn: the values that hold for the intended build, the handful of faults that come back every week, and what still gets checked before the data leaves. All three are on this page.
Three chapters, in the order the questions come up: first the rules for the build you intend, then the faults we actually meet in incoming data, last the list to work through before release. Jump straight to whichever chapter you need.
Nothing decides the cost and the reliability of a board as much as the layout does. The rules below are the ones that come up again and again in our feasibility reviews, sorted by the build you are working on. They are the standard case — most of them can be pushed further after a review.
Each block gives the values that hold as a standard process, then the one rule that most often costs a revision loop. Anything outside these values is not automatically impossible — it moves the board into the advanced column, which usually means a longer lead time and a higher price rather than a refusal. If two of these parameters are pushed at the same time, ask before you route: the combination is what tends to break, not the individual value.
The ordinary case, and the one where most avoidable cost sits. The build has to be symmetrical about the centre, the copper has to be reasonably evenly spread across each layer, and the drill diameters have to survive the aspect ratio at the finished thickness.
Most common revisionAn asymmetric build warps. If the layer count or the copper distribution forces asymmetry, raise it before layout freeze rather than after first articles — at that point the fix is a new stack-up, not a process tweak.
Aspect ratio8:1 preferred, up to 14:1 (Ø 0.20 mm) / 16:1 (Ø 0.25 mm)
MaterialHigh-Tg recommended from 8 layers
HDI and microvia
[ Laser-drilled ]
HDI buys density, and it charges for it in process steps: every sequential lamination cycle is another pass through the plant. The build notation says how many of those you are paying for — 1+N+1 is one, 2+N+2 is two.
Most common revisionStacked microvias need filled and capped vias underneath and a reliability case to go with them. If the routing works staggered, staggered is cheaper and more robust — the density gain from stacking is smaller than it looks on the layout.
The rigid sections behave like an ordinary multilayer. Everything interesting happens in the transition zone and in the bend, where the board is a mechanical part rather than an electrical one.
Most common revisionNo plated hole in the transition between rigid and flexible zone. Bending stress peaks exactly there, and a barrel is the first thing to crack. Keep vias a clear distance back into the rigid section.
Tracks in the bendperpendicular to the bend axis, no change of width
Semi-flex
[ Bend to fit ]
Semi-flex is FR-4 milled down to a thin remaining layer so it can be bent once into position during assembly. It is markedly cheaper than rigid-flex and it is not a substitute for it: this is a bend-to-install feature, not a moving joint.
Most common revisionSpecify the bend zone as a defined area in the data, not as a note on the drawing. Depth milling is a controlled process and it needs the zone, the target remaining thickness and the bend direction to be unambiguous.
Bend radiusper remaining thickness, stated per design
Bend zoneno plated holes, no component pads
Protectionflexible resist over the bend zone
Via protection
[ Tenting to filling ]
Four different things get called "closing a via" and they cost four different amounts. Which one you need follows from assembly, not from preference: whether the via sits in a pad, whether it has to carry heat, and whether the board is wave-soldered.
Most common revisionNever close a via from one side only. The trapped chemistry has nowhere to go and outgasses during soldering, which shows up as voids under the component and is not repairable.
Tentingone or both sides, solder resist over the pad
Pluggingsolder resist, non-conductive
Filling + cappingvia-in-pad, plated flat
Thermal viasfilled, for heat dissipation
Standardtented both sides unless specified
Stack-up and impedance
[ Controlled ]
An impedance requirement is a requirement on the stack-up, not on the track. Give us the target and the tolerance and let the build-up be calculated against it — a track width fixed in the layout before the stack-up exists usually has to be redrawn.
Most common revisionA controlled layer needs a test coupon in the panel. It costs panel area and it is the only piece of evidence either side has if the impedance is later disputed — leave room for it.
Referencecontinuous reference plane under the controlled layer
Custom buildafter review, + 2 working days
Heavy copper
[ 70 µm and up ]
Thick copper etches at an angle. The gap you draw is not the gap you get, and the thicker the foil the bigger the difference — which is why the track and gap minimums climb with copper weight rather than staying put.
Most common revisionHatch large copper areas. An even copper distribution across the layer is what makes plating even; a solid pour next to an empty region gives you thickness variation and, on the laminate, warpage.
Solder resistthicker copper needs more resist over the edge
Mixed weightspossible, layer by layer, after review
Thirteen faults we find every week
[ Chapter 02 ]
These are not exotic. Almost every data set that comes back with a query fails on one of the thirteen points below, and most of them cost a day rather than a redesign — provided they are caught before tooling rather than after.
A CAM department can correct a great deal silently, and most of them do. We would rather tell you: a silent correction is a change to your board that you did not approve and cannot reproduce next time. Everything below is something we will come back to you about rather than quietly fix.
01
Annular ring too small
What it isThe copper ring left around a drilled hole once the drill has landed at its worst-case position.
Why it failsDrill registration is not perfect and neither is layer registration. Where the ring is already at the minimum in the data, a normal deviation breaks it out and the connection is gone.
What to changePad diameter = final hole diameter + 0.35 mm. Smaller is possible, but then the annular ring is below the standard value and has to be agreed.
02
Plated hole to copper
What it isThe clearance between a plated through hole and unrelated copper on the same layer.
Why it failsThe hole wall is plated, so the copper grows towards the neighbouring feature. At the minimum gap, plating tolerance plus registration produces a short.
What to changeKeep the drill-to-copper distance, not the pad-to-copper distance. Check the clearance against the drill, on every layer, including the planes.
03
Non-plated holes and slots
What it isClearance around NPTH holes and milled slots.
Why it failsA non-plated hole is cut mechanically with a wider tolerance than a plated one, and the cutter breaks out copper it touches.
What to changeGive NPTH features their own, larger keep-out. Never derive it from the PTH rule — the tolerance is not the same.
04
Holes on or beside SMD pads
What it isA via sitting in a component pad, or so close to it that the mask cannot separate them.
Why it failsSolder wicks down an open via during reflow. The joint starves and the fault is invisible from above.
What to changeMove the via off the pad, or specify via-in-pad properly: filled and capped, plated flat. Tenting alone does not solve it.
05
Track width against copper weight
What it isA track and gap combination that the selected base copper cannot etch.
Why it failsThick copper etches at an angle. The gap drawn is not the gap produced, and the difference grows with the foil thickness.
What to changeMatch the minimum to the copper: 75 / 75 µm at 18 and 35 µm, 150 / 200 µm at 70 µm, 180 / 300 µm at 105 µm (outer layers).
06
Stubs and orphan copper
What it isTrack segments that end without connecting to anything.
Why it failsThey etch to a thin filament, lift, and travel with the process fluid onto another part of the panel, where they short something that was drawn correctly.
What to changeRun a connectivity check and delete unconnected segments before export. This is the cheapest fix on the list and the one most often skipped.
07
Slivers and same-net spacing
What it isCopper features that taper to a point, and features on the same net drawn closer than the process minimum.
Why it failsSame-net spacing is usually excluded from the DRC because a short there is harmless electrically. It is not harmless in the plant — the sliver still detaches.
What to changeEnable same-net spacing in the DRC. Break sharp copper transitions with a chamfer rather than a point.
08
Copper to board edge
What it isThe distance from copper to the routed or scored profile.
Why it failsRouting tolerance is ± 0.1 mm and scoring is wider than that. Copper reaching the edge gets cut, burrs, and exposes a path for moisture into the laminate.
What to changeHold a defined copper-to-edge distance all the way round, and increase it on scored edges. If the board needs edge plating, say so — it is a different process, not a tighter tolerance.
09
SMD and BGA pad geometry
What it isPad shapes taken from a library without checking them against the actual component and the assembly process.
Why it failsThe pad decides the solder volume. A pad that is generous in one axis and tight in the other pulls the component out of position during reflow.
What to changeDerive pads from the component drawing, keep them consistent across the footprint, and check the fine-pitch ones against the mask rule below.
10
Inconsistent solder mask oversize
What it isSome pads drawn with mask oversize and others without, in the same data set.
Why it failsIt reads as intent. CAM cannot tell a deliberate mask-defined pad from an oversight, so it has to ask — and asking costs a day.
What to changeBe consistent, and state the intended oversize once in the specification. Where a pad is deliberately mask-defined, mark it as such.
11
Solder mask dam too narrow
What it isThe strip of resist left standing between two adjacent pads.
Why it failsBelow the process minimum the dam does not survive developing. It washes away and the two pads bridge during assembly.
What to changeHold ≥ 100 µm as standard, and go wider with ENIG or immersion tin — both attack the resist more aggressively.
12
Solder mask coverage
What it isOpenings that expose more copper than intended, or cover something that has to stay solderable.
Why it failsExposed copper next to a joint invites bridging and corrodes; masked-over test points fail the electrical test through no fault of the board.
What to changeCheck the mask layer against the assembly drawing, not against the copper layer. Test points, fiducials and edge connectors need openings.
13
Legend print over pads
What it isSilkscreen falling onto solderable areas, or characters below the printable size.
Why it failsInk on a pad prevents wetting. Characters under the minimum height print as a smudge and cannot be read at inspection, which is the only reason they exist.
What to changeClip the legend off every solderable surface and hold character height ≥ 0.8 mm. If the board is too dense for a legend, drop it deliberately rather than printing it illegibly.
Checklist before you hand over data
[ Chapter 03 ]
The point of a checklist is not that any single item is difficult. It is that the one you skip is the one that comes back three weeks later as a query, when the schedule no longer has room for it. Work down the list; it takes about twenty minutes on a board you know well.
Run it at release, not at layout freeze — the two are rarely the same moment, and most of what goes wrong is introduced between them. If your team already has a checklist, use that one and take from here only what it is missing; two competing lists are worse than one imperfect one.
01
Component packaging
Every footprint traced back to the current component drawing, not to an inherited library entry
Pad geometry consistent across the footprint and matched to the assembly process
Polarity and pin 1 marked on the copper as well as the legend
Obsolete or single-source parts flagged before the layout depends on their outline
02
Placement
Connectors and mounting points located from the mechanical model, not from the schematic
Enough clearance around tall components for the assembly tooling
Thermally hot parts spread rather than clustered against a board edge
Component orientation consistent enough for the placement machine and for visual inspection
03
Mechanical
Board outline checked against the enclosure using a 3D model, not a dimension list
Cut-outs and slots given radii the cutter can actually produce
Mounting holes correct as plated or non-plated, with the right keep-out for each
Panel or delivery format agreed if the assembler needs one
04
Technical
Layer count and stack-up fixed and symmetrical
Base material chosen for the solder cycles and the operating temperature, not by default
Finished thickness and copper weights stated per layer
Surface finish chosen for the fine-pitch parts on the board
05
Constraint rules
Minimum track and gap matched to the base copper weight
Drill-to-copper clearances set against the drill, not the pad
Same-net spacing enabled rather than excluded
Impedance classes defined as rules, with the target and tolerance stated
06
Routing
No unconnected stubs or orphan copper anywhere in the data
Copper-to-edge distance held all the way round the profile
Large copper areas hatched or otherwise balanced across the layer
No plated hole in a rigid-flex transition zone or a semi-flex bend area
07
Timing
Length-matched groups actually matched after the last routing change
Reference plane continuous under every controlled-impedance track
Return paths checked where a signal changes layer
Clock and high-speed lines kept clear of the board edge and of each other
08
Power
Copper cross-section sized for the current, at the operating temperature
Decoupling placed against the pin it decouples, not against the plane
Plane splits checked so no signal crosses one
Thermal vias specified as filled where they carry heat rather than current
09
DRC
DRC run clean on the released data, not on the version before the last edit
Every waived violation documented with a reason
Netlist compared against the schematic after the final change
Manufacturing rules checked as well as electrical ones
10
Test
Test points accessible and not covered by solder mask
Test point size and pitch within the fixture capability
Impedance coupon given room in the panel where a layer is controlled
Electrical test scope agreed if it goes beyond 100 % net testing
11
Silkscreen
Legend clipped off every solderable surface
Character height ≥ 0.8 mm throughout
Reference designators readable in the assembled orientation
Required markings present: UL, date code, revision, factory field
12
Data review
Output regenerated after the last edit, not reused from an earlier run
Layer names and drill file mapping unambiguous to someone who has not seen the board
Drawing, stack-up and specification consistent with the copper data
Data opened once in a viewer and looked at, as a stranger would see it
Take it with you
The checklist and the underlying design rules are in the capability documents in the download centre. No registration, no form.
Single values are rarely the problem — combinations are. Send the intended build and we will tell you which of them is the binding constraint before you route.