01
Via
Vias
Plated holes connect layers. Diameter and aspect ratio determine how reliably the hole can be plated.
Min. Ø
0.10 mm
Aspect ratio
up to 16 : 1
Annular ring
≥ 75 µm
Rule
Pad Ø = final diameter + 0.35 mm. Smaller pads reduce the annular ring below the standard value.
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02
Via
Via Plugging
Closing the hole with solder resist or conductive paste — stops solder paste wicking into the via during assembly.
Method
Tenting / plugging / filling
Fill
non-conductive standard
Via-in-pad
filled + capped
Rule
Never close vias from one side only — trapped chemistry outgasses during soldering and creates voids.
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03
Via
Microvia
Laser-drilled micro holes for HDI build-ups. They connect adjacent layers in minimal space.
Min. Ø
0.10 mm
Depth
1 layer
Stacking
stacked / staggered
Rule
Stacked microvias need filled and capped target pads. Staggered layout is more process-reliable and cheaper.
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04
Via
Blind / Buried
Buried and blind holes connect only selected layers — they create routing space in dense multilayers.
Blind
outer to inner layer
Buried
inner layers only
Drill cycles
each cycle adds cost
Rule
Every additional drill and press cycle costs lead time. Fix the number of sequences early with the stack-up.
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05
Surface
Surface Finishes
ENIG, immersion tin, HASL, OSP and hard gold — the choice follows pitch, soldering process and storage time.
ENIG
Au 0.025 – 0.075 µm
Imm. tin
0.8 – 1.2 µm
Shelf life
6 – 12 months
Rule
HASL is unsuitable below 0.5 mm pitch and for HDI — the uneven topography causes bridging.
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06
Surface
Solder Mask
Protects the tracks and defines solderable areas. The minimum dam between two pads limits how fine assembly can go.
Standard
IPC-SM-840 Cl. T
Dam
from 70 µm, by colour
Colours
green, black, white, blue
Rule
With ENIG and immersion tin allow a wider dam — both processes attack the resist more aggressively.
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07
Surface
Wire Bonding
Bondable surfaces for direct die attach. Requires defined roughness and cleanliness of the bond pads.
Finish
ENEPIG / hard gold
Au thickness
< 0.1 µm on ENEPIG
Wire
gold / aluminium
Rule
Bond pads must not overlap solder resist and need a larger clearance than normal pads.
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08
Surface
IC Substrate
Ultra-fine line carriers for direct die mounting — the most demanding structure class in the portfolio.
Structure
on request
Flatness
tightly toleranced
Build
per feasibility review
Rule
IC substrates require a feasibility review before layout. Please involve engineering early.
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09
Signal
Impedance Control
Defined characteristic impedance via stack-up and trace geometry — a prerequisite for high-speed and RF designs.
Single-ended
50 Ω
Differential
90 / 100 Ω
Tolerance
± 10 %
Rule
Impedance-controlled layers need a test coupon in the panel — it is the only evidence in a complaint.
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10
Signal
High Frequency
RF materials with low loss factor and stable dielectric constant for radar and antenna applications.
Dk
3.0 – 3.6
Df
< 0.004
Build
hybrid possible
Rule
Hybrid build-ups of RF material and FR-4 cut cost noticeably — only the critical layers need the expensive material.
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11
Power
Heavy Copper
Reinforced copper layers for high currents and better heat dissipation in power electronics.
Final copper
70 – 140 µm
Structure
from 150 / 200 µm
Layers
outer and inner
Rule
As copper thickness rises, track and gap must grow with it — the etch flank becomes shallower and wider.
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