The capability extract shows in thirty seconds what runs as standard and what carries a surcharge.
See capabilities →Send the files and an engineer reviews them against your build — free, before you enquire.
To the data check →Impedance is not something we measure after the fact and hope for. It is designed into the stack-up, compensated for in the artwork, and verified on a coupon in every panel. All three steps have to happen or the number on the drawing means nothing.
Three things happen between your data and a controlled board. First, we calculate the stack-up backwards from your target impedance using the real laminate data, adjusting dielectric thicknesses and proposing corrected track widths where needed. Second, CAM applies etch compensation — the copper is etched from the top, so a track comes out narrower at the top than at the bottom, and the artwork is widened to land on target. Third, a TDR coupon in the panel is measured per lot.
The step designers most often get wrong is the second one. Widening tracks yourself to compensate for etching means the compensation gets applied twice and the finished impedance comes out low. Send the target, not a pre-corrected geometry.
The stack-up is worked back from the target impedance with real laminate data and sent for approval before tooling.
Etch compensation is applied by us. It is a production parameter, not something the designer should pre-empt.
A TDR coupon rides in every panel and is measured per lot. The measurement report is available on request.
| Parameter | Standard | Advanced | Note |
|---|---|---|---|
| Single-ended | 50 Ω | 40 – 120 Ω | Other targets on request |
| Differential | 90 / 100 Ω | 85 – 120 Ω | USB, Ethernet, LVDS, PCIe |
| Tolerance | ± 10 % | on review | Tighter tolerances are subject to technical review |
| Frequency range | ≤ 5 GHz | ≤ 20 GHz | Above this material Dk stability dominates |
| Coupon | per panel | per panel | TDR measured; report on request |
| Reference plane | adjacent | dual | Solid, unbroken, on the adjacent layer |
| Etch compensation | by us | by us | Do not pre-compensate your artwork |
| Stack-up approval | before tooling | before tooling | Sent as a calculated build |
Guide values for pre-selection. Binding values are confirmed per project against your data.
The points below are what most often comes back as a query after data review. Settling them before layout freeze saves a loop.
A controlled track crossing a gap in its reference plane loses its impedance at that point. This is the most common signal-integrity failure and it is a routing decision, not a manufacturing one.
Etch compensation is applied in CAM. Widening the tracks yourself gets it applied twice and the finished impedance comes out below target.
Target, tolerance and the layers concerned. Requirements that exist only in the schematic or an email do not reach the production floor.
The coupon needs room in the border. In series panels this costs nothing; in tight prototype panels it can cost a copy of the board.
We publish ± 10 %. Anything tighter constrains etch tolerance and dielectric thickness across the whole panel, so it is subject to a technical review of stack-up and material — confirmed per design, not promised as a figure.
Yes, and we prefer to. Send target impedances, layer assignment and layer count; you get a calculated build back for approval before tooling.
On impedance-controlled jobs, yes. It is the only objective evidence of what was built, which matters if performance is ever questioned.
Increasingly with frequency. FR-4 Dk drifts with frequency and temperature; above a few GHz that drift is larger than the impedance tolerance you are asking for, and a low-loss or RF laminate becomes necessary.
Send us your data or a rough sketch. We check feasibility, name the cost drivers and answer within one working day.